CMOS Scaling for High Performance and Low Power-The Next Ten Years

A guideline for scaling of CMOS technology for logic applications such as microprocessors is presented covering the next ten years, assuming that the lithography and base process development driven by DRAM continues on the same three-year cycle as in the past. This paper emphasizes the importance of optimizing the choice of power-supply voltage. Two CMOS device and voltage scaling scenarios are described, one optimized for highest speed and the other trading offspeed improvement for much lower power. It is shown that the low power scenario is quite close to the original constant electric-field scaling theory. CMOS technologies ranging from 0.25 pm channel length at 2.5 V down to sub-0.1 p m at 1 V are presented and power density is compared for the two scenarios. Scaling of the threshold voltage along with the powersupply voltage will lead to a substantial rise in standby power compared to active power, and some tradeoffs of performance andor changes in design methods must be made. Key technology elements and their impact on scaling are discussed. It is shown that a speed improvement of about 7x and over two orders of magnitude improvement in power-delay product (mW/MlPS) are expected by scaling of bulk CMOS down to the sub-0.1 pm regime as compared with today's high performance 0.6 p m devices at 5 V. However, the power density rises by a factor of 4 X for the high-speed scenario. The status of the siliconon-insulator (Sol) approach to scaled CMOS is also reviewed, showing the potential for about 3x savings in power compared to the bulk case at the same speed.